(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a clock skew test circuit and, more particularly, to a semiconductor integrated circuit including a test circuit for measuring a clock skew in a synchronous logic circuit.
(b) Description of the Related Art
Semiconductor integrated circuits operating in a synchronous mode are used in recent electronic apparatus such as personal computers, because such semiconductor integrated circuits can reduce the size of electronic apparatus and the power consumption thereof.
FIG. 1 is a schematic plan view of a conventional semiconductor integrated circuit operating in a synchronous mode for a specified function and formed on a main surface of a semiconductor substrate. As shown in FIG. 1, the conventional semiconductor integrated circuit 600 has clock input pin 101 for receiving a clock signal, main clock buffer 102 having an input connected to clock input pin 101, clock lines 103, 551, 552, and 553 extending from the output of main clock buffer 102 to drive secondary clock buffers 104, 105 and 106, each for providing the clock signal to corresponding one of clock lines.
The conventional semiconductor integrated circuit 600 includes clock line 122, clock node 568 of clock line 122, clock line 125 extending from the output of secondary clock buffer 106 to drive flip flops 119 and 121, clock line 516 extending from the out put of secondary clock buffer 105 to drive flip flops 508, 510 and 512, clock node 567 of clock line 516 connected to the clock input of flip flop 512, clock line 124 extending from the output of secondary clock buffer 104 to drive flip flops 108, 110 and 112, clock node 565 of clock line 124 connected to the clock input of flip flop 112. The flip flops 119 and 121, the flip flops 508, 510, and 512, and the flip flops 108, 109 and 110 constitute, for example, a frequency divider and registers, respectively.
The semiconductor integrated circuit 600 has inverters 114 and 115 which receive output 113 from flip flop 112, I/O buffer 116 which receives and amplifies output from inverter 115 to generate an output signal, I/O buffer 514 which receives and amplifies output 513 from flip flop 512 to generate an output signal, inverters 518 and 519 which receive output 517 from flip flop 121, and I/O buffer 520 which receives and amplifies output from inverter 519 to generate an output signal. I/O buffers 116, 514 and 520 are controlled by an external control signal 522 received through a control pin 523.
In the conventional semiconductor integrated circuit 600, the clock signal received through clock input pin 101 is transmitted to clock node 565 via main clock buffer 102, clock line 103, clock node 562, clock line 552, clock node 563, clock line 553, clock node 564, secondary clock buffer 104 and clock line 124. The propagation delay of the clock signal from clock input 101 to clock node 565 is the largest in the semiconductor integrated circuit 600.
By contrast, the clock signal is transmitted from clock input pin 101 to clock node 568 via main clock buffer 102, clock line 103, clock node 562, clock line 551, clock node 561, secondary clock buffer 106 and clock line 122. The propagation delay of the clock signal from clock input pin 101 to clock node 568 is the smallest in the semiconductor integrated circuit 600.
The propagation delay of the clock signal in the semiconductor integrated circuit 600 will be described with reference to FIG. 2.
When the clock signal supplied from the outside to clock input pin 101 rises at time instant t0, the signal level at clock node 568 rises at time instant t1. Namely, a propagation delay tpdl (=t1-t0) is produced. At time instant t2, the signal level at clock node 565 rises so that flip flop 112 operates synchronously with the clock signal. Namely, a propagation delay tpd2 (=t2-t0) is produced, thereby generating a clock skew .DELTA.T (=tpd2-tpd1).
As a result, the synchronous logic circuit of the semiconductor integrated circuit 600 operates under the clock skew .DELTA.T corresponding to the difference in the propagation delay of the clock signal between clock nodes 568 and 565.
Under the clock skew produced in a conventional semiconductor integrated circuit, it is desirable to measure the maximum operational speed of the logic circuit so as to guarantee stable operation. For instance, Patent Publication JP-A-2-232575 describes a test circuit for measuring the operational speed of a logic circuit.
In the conventional test circuit of FIG. 3 described in the publication as mentioned above, a test signal 807 supplied through a test signal input pin 801 is transmitted to a delay circuit 808 such as a flip flop circuit to be tested, via transfer gate 802 having a gate receiving a clock signal .phi.1. The output of the delay circuit 803 is connected to a first input of an exclusive OR gate 805 via a transfer gate 804 having a gate receiving a clock signal .phi.2. Also, the test signal 807 supplied through the test signal input pin 801 is directly transmitted to a second input of the exclusive OR gate 805. With this structure, the propagation delay of the delay circuit 803 can be determined.
If the test circuit as described above is included in the semiconductor integrated circuit 600 operating in a synchronous mode and a clock test for measuring the operational speed is performed to verify the clock skew to be within a predetermined range, the stable operation of the semiconductor integrated circuit device can be verified.
Recent electronic apparatus requires a semiconductor integrated circuit of a larger scale having up to 1 million gates per a chip. The propagation delay of the clock signal depends on the planar layout of the semiconductor integrated circuit and the clock skew increases as the scale of the integration increases. Electronic apparatuses are required to operate at a clock frequency of up to approximately 100 MHz. Therefore, it is desirable to measure and determine a clock skew so as to guarantee an adequate operation.
That is, a test circuit such as described above is desired in an LSI. However, even when the conventional test circuit is included in a semiconductor integrated circuit, the value of the clock skew itself cannot be determined for a function circuit. Hence, it is difficult to provide a semiconductor integrated circuit having a stable synchronous logic circuit.